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Ordering number : EN *5428A
CMOS LSI
LC89086M
8 Bit A/D Converter
Preliminary Overview
The LC89086M is a low-power high-speed 8-bit serialparallel A/D converter fabricated in a high-speed CMOS process.
Package Dimensions
unit: mm 3155-MFP24
[LC89086M]
Features
* * * * * * * Resolution: 8 bits (with an overflow output) Maximum conversion rate: 20M samples per second Error: Less than 1.0 LSB Power supply: +5-V single-voltage power supply Power dissipation: 150 mW (typical) Analog input voltage range: VSS to VDD Digital output voltage: 3 state TTL level
SANYO: MFP24
Specifications
Absolute Maximum Ratings at Ta = 25C, DVSS = AVSS = 0 V
Parameter Maximum supply voltage Input voltage Operating temperature Storage temperature Symbol VDD max VIN max Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD +0.3 -30 to +70 -40 to +125 Unit V V C C
Recommended Operating Conditions
Parameter Supply voltage Operating ambient temperature Symbol VDD Ta Conditions Ratings min 4.5 -30 typ 5.0 max 5.5 +70 Unit V C
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O3097HA (OT) No. 5428-1/6
LC89086M
Electrical Characteristics
Electrical DC Characteristics at Ta = -30 to +70C, AVDD = DVDD = 4.5 to 5.5 V, AVSS = DVSS = 0 V
Parameter Reference resistance Analog input capacitance Analog input resistance Reference high-level input voltage Reference low-level input voltage Reference high-level output voltage Symbol Rref CAIN RAIN VrefH VrefL VrefH When VrefHO (pin 4) and VrefLO (pin 9) are unused. Vref L + 2.0 0 1.9 2.0 Conditions VrefH (pin 5) - VrefL (pin 8) Ratings min 210 typ 300 30 10 VDD VrefH - 2.0 2.1 max 390 Unit pF M V V V
When VrefHO (pin 4) and VrefLO (pin 9) are unused. When VrefHO (pin 4) and VrefLO (pin 9) are used, and AVDD = DVDD = 5 V When VrefHO (pin 4) and VrefLO (pin 9) are used, and AVDD = DVDD = 5 V
Reference low-level output voltage Analog input voltage Digital high-level voltage Digital low-level voltage Digital high-level output current Digital low-level output current
VrefL VAIN VIH VIL IOH IOL
-0.05 VrefL 2.2 -0.3
0
+0.05 VrefH VDD +0.3 +0.8
V V V V mA mA
VOH = VDD - 0.4 V VOL = 0.4 V
-2 2
Electrical AC Characteristics 1 at Ta = -30 to +70C, AVDD = DVDD = 4.5 to 5.5 V, AVSS = DVSS = 0 V
Parameter Clock high-level period Clock low-level period Analog input acquisition time Digital output data delay time Digital output data enable time Digital output data disable time Symbol TWH TWL TAP Td TOE TOD C load = 30 pF C load = 30 pF C load = 30 pF Conditions Ratings min 23 23 10 15 2 2 20 30 5 5 30 45 10 10 typ max Unit ns ns ns ns ns ns
No. 5428-2/6
LC89086M Timing Chart
Clock input (CLK) TWH Analog input (AIN) TWL TAP
1.5 V
N+3 N N+1 Td N+2
Digital output (D8 to D1,OF)
N-4
N-3
N -2
N-1
1.5 V
N
Output enable input (OEB) TOE
1.5V TOD
Digital output (D8 to D1,OF)
High impedance
A09018
The analog signal (AIN) is acquired on the falling edge of the clock input (CLK). The acquired analog signal is converted to a digital code and is output from the digital outputs (D8 to D1, OF) on the clock falling edge delayed three clock cycles from the clock cycle in which the analog signal was acquired.
Electrical AC Characteristics 2 at Ta = 25C, AVDD = DVDD = 5 V, AVSS = DVSS = 0 V, VrefH = 2 V, VrefL = 0 V
Parameter Resolution Maximum conversion rate Linearity error Differential linearity error Offset voltage Power dissipation Symbol Res Fs LE DLE Voffset Pd DC accuracy DC accuracy DC accuracy Fs = 20 MSPS 10 50 150 Conditions Ratings min typ max 8 20 1.0 1.0 90 220 Unit bit MSPS LSB LSB mV mW
Note: Test circuits must conform to the sample application circuit.
No. 5428-3/6
LC89086M Block Diagram
OEB 1
Upper encoder
Lower Vref selection
22
OF
AIN
6
Upper comparator
Data correction
VrefH
5
Lower comparator
VrefM
7
Resistor string
Lower encoder
Output register
21
D1(MSB)
14
D8(LSB)
VrefL
8
Reference voltage generation
Clock generation
23
CLK
4 VrefHO
9 VrefLO
A09019
Pin Assignment
Top view
No. 5428-4/6
LC89086M Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin name OEB DVSS AVSS Vref HO Vref H AIN Vref M Vref L Vref LO AVDD AVSS DVSS DVDD D8 D7 D6 D5 D4 D3 D2 D1 OF CLK DVDD O O O O O O O O O I O I I O I O I/O I Digital output enable input High: high-impedance Low: Normal operation Digital ground Analog ground Internal reference voltage (high) generation. Shorting this pin to VrefH (pin 5) generates a voltage of 2.0 V. This pin must be left open when the internally generated potential is not used. Reference voltage input (high) Analog input Reference voltage intermediate level tap. Reference voltage input (low) Internal reference voltage (low) generation. Shorting this pin to VrefL (pin 8) generates a voltage of 0 V. This pin must be left open when the internally generated potential is not used. Analog power supply Analog ground Digital ground Digital power supply Digital output (LSB) Digital output Digital output Digital output Digital output Digital output Digital output Digital output (MSB) Digital output (Overflow) Clock input Digital power supply Function
Note: There must be no potential difference between the digital system and analog system VDD and VSS power supply potentials.
I/O Code Table The table below lists the relationship between the input and output when VrefH and VrefL are set up so that the zero transient voltage is 0.000 V and the full-scale transient voltage is 2.008V.
Analog input VAIN (V) Up to 0.000 Up to 0.008 Up to 0.016 Up to 0.024 Up to 0.032 OF 0 0 0 0 0 D1 0 0 0 0 0 D2 0 0 0 0 0 D3 0 0 0 0 0 Digital output D4 0 0 0 0 0 D5 0 0 0 0 0 D6 0 0 0 0 0 D7 0 0 0 1 1 D8 0 0 1 0 1
to
Up to 0.992 Up to 1.000 Up to 1.008 Up to 1.016
0 0 0 0
0 0 1 1
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
0 1 0 1
to
Up to 1.992 Up to 2.000 Up to 2.008 Over 2.008
0 0 0 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 1 1 1
1 0 1 1
No. 5428-5/6
LC89086M Sample Application Circuit
: Digital VDD(5V)
100 0.01 100 0.01
: Analog VDD(5V) : Digital Ground
Output enable in
1 OEB 2 DVSS
DVDD 24 CLK 23 OF 22 D1 (MSB) 21 Clock in Overflow flag out
: Analog Ground
*1 3 AVSS
100 0.01
4 VrefHO 5 VrefH
LC 89086M
D2 20 D3 19 D4 18 Digital out D5 17 D6 16 D7 15 D8 (LSB) 14 DVDD 13 Unit (capacitance: F)
Analog in
*2
10
6 AIN CLAMP 7 VrefM 8 VrefL
100 0.01
9 VrefLO 10 AVDD 11 AVSS 12 DVSS
1
*1
Note 1. The value of the reference resistor is about 300 . When this circuit is used with (VrefH - VrefL) = 2 V, a current of 6.7 mA will flow. Use an operational amplifier or emitter follower with at least this current capacity. 2. The analog input impedance is lower for AC inputs. Therefore, an operational amplifier or emitter follower with a high slew rate and a wide bandwidth must be used in the previous stage output, and the impedance must be reduced to under 100 .
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 1997. Specifications and information herein are subject to change without notice. No. 5428-6/6

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